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BlackByte

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About the ESP32 Technical Reference Manual
« on: February 28, 2018, 10:34:50 PM »
Here is the main content of the technical manual for the ESP32.

In this topic we will study the ESP32 features.

1.- System and Memory Ready
2.- Interrupt Matrix Ready
3.- Reset and Clock Ready
4.- IO_MUX and GPIO Matrix Ready
5.- DPort Register Ready
6.- DMA Controller Ready
7.- SPI Ready
8.- SDIO Slave Ready
9.- SD/MMC Host Controller Ready
10.- I2C Ready
11.- I2S Ready
12.- UART Controllers Ready
13.- LED_PWM Ready
14.- Remote Controller Peripheral Ready
15.- MCPWM Ready
16.- PULSE_CNP Ready
17.- 64-bit Timers Ready
18.- Watchdog Timers Ready
19.- eFuse Controller Ready
20.- AES Accelerator Ready
21.- SHA Accelerator Ready
22.- RSA Accelerator Ready
23.- Random Number Generator Ready
24.- Flash Encryption/Decryption Ready
25.- PID/MPU/MMU Ready
26.- PID Controller Ready
27.- On-Chip Sensors and Analog Signal Processing Ready
28.- ULP Co-processor Ready
29.- Low-Power Management Ready

Once you have learn a little bit more about ESP32 features you can learn how to install the ESP32 Development framework in the link below.

ESP32 APIs and Toolchain Installation http://thebytespace.cl/smf/index.php?topic=18.0

Why i present this information?

- Because i have decided to learn this tools in this year, and i have some experience programming other tools before, so i decided to start this study knowing what this caracteristics are one by one, and then going deeper on every one after, this way we will be going from general to specific, this way we can do a mental image about the system from beginning.

- If this is your first time programming a MCU (Micro controller Unit) and you want to undestand more about what is going on here, i recommend you to learn about Microcontroller architecture, and what this things are and what are they  capable of.
« Last Edit: April 06, 2018, 07:51:58 PM by BlackByte »
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BlackByte

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About "System and Memory" on the ESP32 Technical Reference Manual
« Reply #1 on: March 02, 2018, 04:30:48 AM »
Overview
1.- System and Memory.

- So ESP32 is a dual-core system, both Harvard architecture (Xtensa LX6 CPUs).

- Memory (both of them, embedded and external memory) and peripherals are located on the data bus and/or the instruction bus of these CPUs.

- Theaddress mapping of two CPUs is symmetric, that means both access the same memory with same addresses (with some minor exceptions).

- Many perihperals in the system can access embedded memory via DMA (Direct Memory Access).

- There is a protocol CPU named 'PRO_CPU' and an application CPU named 'APP_CPU' and they are however interchangeable for most purposes.
« Last Edit: March 16, 2018, 03:12:33 PM by BlackByte »
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About "Imterrupt Matrix" on the ESP32 Technical Reference Manual
« Reply #2 on: March 02, 2018, 02:56:10 PM »
Overview
2.- Interrupt Matrix

- The Interrupt Matrix embedded in the ESP32 independently allocates peripheral interrupt sources to the two CPUs perihperal interrupts so this way is flexible to meet many different needs.

- It acepts 71 peripheral interrupt sources as input.

- Every CPU can generates 26 peripheral interrupt sources as output (52 in total).

- There is an "NMI" interrupt mask

- You can query the current interrupt status of perihperal interrupt sources.
« Last Edit: March 21, 2018, 05:31:12 PM by BlackByte »
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About "Reset and CLock" on the ESP32 Technical Reference Manual
« Reply #3 on: March 02, 2018, 03:29:43 PM »
Overview
3. Reset and Clock

3.1 System Reset

- ESP32 has three reset levels:
 
 1- System itself (Core + RTC)
 2- Only Core reset (CPU + WIFI + Bluetooth + DIG GPIO + PERI). 'subsystem'
 3- Just CPU reset (Central Processing Unit) 'subsystem'

- In system reset, all the registers on the chip, including those of the RTC are reset.

- In core reset, all the digital registers, including CPU cores, external GPIO and digital GPIO. (Not the RTC registers).

- In CPU reset, only the registers of the CPUs are reset 'both or just one'.

**Reset could mean set to default values or clear or erased**

3.2 System Clock.

 - ESP32 integrates multiple clock sources for the CPU cores, perihperals and the RTC.
This clocks can be configured to meet different requirements. (High Speed Clocks, Low Power Clocks and Audio CLock).
« Last Edit: March 21, 2018, 05:30:49 PM by BlackByte »
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About "IO_MUX" on the ESP32 Technical Reference Manual
« Reply #4 on: March 03, 2018, 04:03:29 PM »
Overview
4. Input Output Multiplexor (IO_MUX) and General Prupose Input Output Matrix (GPIO Matrix)

The esp32 has 34 physical pads for input or output called GPIO "General Purpose Input Output".

Each pad can be used as a general-purpose Input/Output, or be connected to an internal peripheral signal. The IO_MUX (IO Multiplexor), RTC IO_MUX (RTC IO Multiplexor) and GPIO matrix are responsible for routing signals from the peripherals to GPIO pads providing configurable Input/outputs.
« Last Edit: March 21, 2018, 05:30:21 PM by BlackByte »
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About "DPort Register" on the ESP32 Technical Reference Manual
« Reply #5 on: March 05, 2018, 01:55:23 AM »
Overview
5. DPort Register.

The DPort registers control clock management (clock gating), power management, and the configuration of peripherals and core system modules.

"The system configures each module via the configuration registers in DPort Register."

DPort registers correspond to different peripherals blocks and core modules:

 - System and memory
 - Reset and clock
 - Interrupt matrix
 - DMA (Direct Memory Access)
 - PID/MPU/MMU
 - Peripheral clock gating and reset.
« Last Edit: March 21, 2018, 05:31:49 PM by BlackByte »
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About "DMA Controller" the ESP32 Technical Reference Manual
« Reply #6 on: March 05, 2018, 02:50:13 AM »
Overview
6. DMA controller

 Direct Memory Access is used for high-speed data transfer between perihperals and memory as well as memory to memory.

 Data can be quickly moved by DMA without any CPU intervention, thus allowing for more efficient use of the cores for data processing.

 In the ESP32, 13 peripherals are capable of DMA for data transfer, namely:

 - UART(0,1,2)
 - SPI(1,2,3)
 - I2S(0,1)
 - SDIO slave
 - SD/MMC host
 - EMAC
 - BT
 - Wi-Fi
« Last Edit: March 21, 2018, 05:32:38 PM by BlackByte »
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About "SPI" the ESP32 Technical Reference Manual
« Reply #7 on: March 08, 2018, 07:10:07 PM »
Overview
7.SPI (Serial Peripheral Interface)

ESP32 integrates four SPI controllers. (SPI<0,1,2,3>)

SPI<0> is used as a buffer for accessing external memory.
SPI<1> can be used as a MASTER
SPI<2> can be configured as either a MASTER or a SLAVE.
SPI<3> can be configured as either a MASTER or a SLAVE.

When used as a MASTER, each SPI controller can drive multiple CS signals (CS0  - CS2) to activate multiple SLAVES.

Controllers SPI1,SPI2 & SPI3 share two DMA channels.(chan0 & chan1).

-

The SPI controller supports four-lines.
- MOSI (Master Output - Slave Input)
- MISO (Master Input - Slave Output)
- CS (Chip Select)
- CLK (Clock)

The full-duplex uses four of them. (MOSI/MISO/CS/CLK)
The half-duplex uses three of them. (MOSI/CS/CLK).
in GP-SPI mode.

In QSPI mode a SPI controller accesses the flash or SRAM by using signal buses D, Q, CS0-CS2, CLK, WP and HD as a four-bit parallel SPI bus.

(Consult "Table 24: SPI Signal and Pin Signal Function Mapping)
Technical reference manual Page 116.

Find more about SPI port. https://es.wikipedia.org/wiki/Serial_Peripheral_Interface
« Last Edit: March 21, 2018, 05:33:29 PM by BlackByte »
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About "SDIO Slave" on the ESP32 Technical Reference Manual
« Reply #8 on: March 09, 2018, 03:55:26 PM »
Overview
8.SDIO Slave (Secure Digital Input/Output)

- The ESP32 features hardware support for the industry-standard Secure Digital device interface that conforms to the SDIO Specification Version 2.0. This allows a host controller to access the ESP32 via an SDIO bus protocol, enabling high-speed data transfer.

- The SDIO interface may be used to read ESP32 SDIO registers directly and access shared memory via DMA, thus reducing processing overhead while maintaining high performance.

Find out more about SDIO here https://en.wikipedia.org/wiki/Secure_Digital#SDIO_cards

Find out more about SDIO Spacification here https://www.sdcard.org/downloads/pls/


« Last Edit: March 21, 2018, 05:34:10 PM by BlackByte »
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BlackByte

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Re: About the ESP32 Technical Reference Manual
« Reply #9 on: March 09, 2018, 09:52:09 PM »
Overview
9. SD/MMC Host Controller

- The ESP32 memory card interface controller provides a hardware interface between the Advanced Peripheral Bus (APB) and an external memory device. The memory card interface alllows the ESP32 to be connected to SDIO memory cards, MMC cards (MultiMediaCard) and devices with a CE-ATA interface. It supports two external cards (Card0 and Card1).

Found more about MMC card here https://en.wikipedia.org/wiki/MultiMediaCard
« Last Edit: March 09, 2018, 09:53:59 PM by BlackByte »
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Re: About the ESP32 Technical Reference Manual
« Reply #10 on: March 09, 2018, 10:04:14 PM »
Overview
10. I2C Controller

- An I2C (Inter-Integrated Circuit) bus can be used for communication with several external devices connected to the same bus as ESP32. The ESP32 has dedicated hardware to communicate with peripherals on the I2C bus.

Found out more about I2C communication here https://en.wikipedia.org/wiki/I%C2%B2C
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Re: About the ESP32 Technical Reference Manual
« Reply #11 on: March 10, 2018, 07:34:50 PM »
Overview
11. I2S (Integrated Interchip Sound)

- The I2S bus provides a flexible communication interface for streaming digital data in multimedia applications, especially digital audio applications. The ESP32 includes two I2S interfaces: I2S0 & I2S1.

- The I2S standard bus define three signals:
  .clock signal
  .serial data signal
  .channel selection signal

- A basic I2S data bus has one master and one slave. The roles remain unchanged throughout the communication.

- The I2S modules on the ESP32 provide separate transmit and receive channels for high performance.

- there are two independent I2S modules embedded in ESP32. Each I2S module contains a Tx(transmit) unit and a Rx(receive) unit. Both the Tx unit and the Rx unit have a three-wire interface that includes a clock line, a channel selection line and a serial data line. The serial data line of the Tx unit is fixed as output, and the serial data line of the receive unit is fixed as input. The clock line an the channel selection line of the Tx and Rx units can be configured to both master transmitting mode and slave receiving mode. In the LCD mode, the serial data line extends to the parallel data bus. Both Tx uni and Rx unit have a 32-bit-wide FIFO with a depth of 64. Besides, only I2S0 supports on-chip DAC/ADC modes, as well as receiving and transmitting PDM signals.

Learn more about PDM modulation here https://en.wikipedia.org/wiki/Pulse-density_modulation

Learn more about I2S here https://en.wikipedia.org/wiki/I%C2%B2S

« Last Edit: March 12, 2018, 02:31:52 AM by BlackByte »
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UART Controllers on ESP32 <i>Overview</i>
« Reply #12 on: March 12, 2018, 03:11:47 AM »
Overview
12. UART Controllers

Embedded applications often require a simple method of exchanging data between devices that need minimal system resources. The Universal Asynchronous Receiver/Transmitter (UART) is one such standard that can realize a flexible full-duplex data exchange among different devices. The three UART controllers available on a chip are compatible with UART-enabled devices from various manufacturers. The UART can also carry out an irDA(Infrared Data Exchange), or function as RS-485 modem.

Find out more about UART here https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter

All UART controllers integrated in the ESP32 feature an identical set of registers for ease of programming and flexibility.
« Last Edit: March 14, 2018, 01:49:53 PM by BlackByte »
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Re: About the ESP32 Technical Reference Manual
« Reply #13 on: March 14, 2018, 02:17:24 PM »
Overview
13. LED_PWM

- The LED_PWM controller is primarily designed to control the intensity of LEDs (Light Emitting Diode), although it can be used to generate PWM (Pulse Width Modulation) signals for other purposes as well. It has 16 channels which can generate independent waveforms that can be used to drive RGB LED devices (Red, Green & Blue color Led). For maximum flexibility, the high-speed as well as the low-speed channels can be driven  from one of four high-speed/low-speed timers. The PWM controller also has the ability to automatically increase or decrease the duty cycle gradually, allowing for fades without any processor interference. To increase resolution, the LED_PWM controller is also able to dither between two values, when a fractional PWM value is configured.

The LED_PWM controller has eight high-speed and eight low-speed PWM generators. These channels can be driven from four timers.

The eight channels (high and low speed) in the technical manual for the ESP32 are referred to as:

  • hschn (high speed channel 'n')
  • lschn (low speed channel 'n')

The four timers (high and low speed) in the technical manual for the ESP32 are referred to as:

  • h_timerx (high speed timer 'x')
  • l_timerx (low speed timer 'x')

Find out more about PWM here https://en.wikipedia.org/wiki/Pulse-width_modulation
« Last Edit: March 14, 2018, 02:23:01 PM by BlackByte »
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About the ESP32 Technical Reference Manual
« Reply #14 on: March 14, 2018, 04:50:14 PM »
Overview
14. Remote Controller Peripheral

- The RMT (Remote Control) module is primarily designed to send and receive infrared remote control signals that use on-off-keying of a carrier frequency, but due to its design it can be used to generate various types of signals. An RMT transmitter does this by reading consecutive duration values for an active and inactive output from the built-in RAM block, optionally modulating it with a carrier wave. A receiver will inspect its input signal, optionally filtering it, and will place the lengths of time the signal is active and inactive in the RAM block.

- The RMT has eight channels.
« Last Edit: March 14, 2018, 04:52:50 PM by BlackByte »
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