Author Topic: About the ESP32 Technical Reference Manual  (Read 1703 times)

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BlackByte

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About the ESP32 'MCPWM' from Manual
« Reply #15 on: March 14, 2018, 05:12:44 PM »
Overview
15. MCPWM

- The Motor Control PWM (MCPWM) peripheral is intended for motor and power control.

- It provides six PWM outputs that can be set up to operate in several topologies.

- One common topology uses a pair of PWM outputs driving an H-bridge to control motor rotation speed and rotation direction.

- The timing an control resources inside are allocated into two major types of submodules: PWM timers and PWM operators.

- Each PWM timer provides timing references that can either run freely or be synced to other timers or external sources.

- Each PWM operator has all necessary control resources to generate waveform pairs for one PWM channel.

- The MCPWM peripheral also contains a dedicated capture submodule that is used in systems where accurate timing of external events is important.

- ESP32 contains two MCPWM peripherals: MCPWM0 and MCPWM1. Their control registers are located in 4-KB memory blocks starting at memory locations 0x3FF5E000 and 0x3FF6C000 respectively.



Learn more about H-bdrige herehttps://en.wikipedia.org/wiki/H_bridge
« Last Edit: March 21, 2018, 05:34:54 PM by BlackByte »
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About "PULSE_CNT" in the ESP32 Technical Reference Manual
« Reply #16 on: March 16, 2018, 02:33:46 PM »
Overview
16.PULSE_CNT

- The Pulse Counter module is designed to count the number of rising and/or falling edges of an input signal. Each pulse counter unit has a 16-bit signed counter register and two channels that can be configured to either increment or decrement the counter. Each channel has a signal input that accepts signal edges to be detected, as well as a control input that can be used to enable or disable the signal input. The inputs have optional filters that can be used to discard unwated glitches in the signal.

- The pulse counter has eight independent units, refered to as PULSE_CNT_Un.
« Last Edit: March 21, 2018, 05:35:05 PM by BlackByte »
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About the 64-bit Timers on ESP32 Technical Reference Manual
« Reply #17 on: March 16, 2018, 02:53:18 PM »
Overview
17. 64-bit Timers

- There are four general-purpose timers embedded in the ESP32. They are all 64-bit generic timers based on 16-bit prescalers and 64-bit auto-capable up/down counters.

- The ESP32 contains two timers modules, each containing two timers. The two timers in a block are indicated by an x in TIMGn_Tx; the blocks themselves are indicated by an n.

 The timers feature:
 - A 16-bit clock prescaler, from 2 to 65536.
 - A 64-bit time-base counter.
 - Configurable up/down time-base counter: incrementing or decrementing.
 - Halt and resume of time-base counter.
 - Auto-reload at alarm
 - Software-controlled instant reload.
 - Level and edge interrupt generation.
« Last Edit: March 16, 2018, 03:50:11 PM by BlackByte »
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BlackByte

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About "Watchdog Timers" on the ESP32.
« Reply #18 on: March 16, 2018, 03:31:23 PM »
Overview
18. Watchdog Timers

- The ESP32 has three watchdog timers: one in each of the two timer modules (called Main system Watchdog Timer, or MWDT) and one in the RTC module (which is called the RTC Watchdog Timer, or RWDT). These watchdog timers are intended to recover from an unforseen fault (not anticipated or predicted fault), causing the application program to abandon its normal sequence. A watchdog timer has four stages. Each stage may take one out of three or four actions upon the expiry of a programmed period of time for this stage, unless the watchdog is fed or disabled. The actions are: interrupt, CPU reset, core reset and system reset. Only the RWDT can trigger the system reset, and is able to reset the entire chip and the main system including the RTC itself. A timeout value can be set for each stage individually.

- During flash boot, the RWDT and the first MWDT start automatically in order to detect and recover from booting problems.

Further information about Watchdog Timers here https://en.wikipedia.org/wiki/Watchdog_timer
« Last Edit: March 16, 2018, 03:50:50 PM by BlackByte »
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About "eFuse Controller" on the ESP32 Technical Reference Manual
« Reply #19 on: March 16, 2018, 04:04:48 PM »
Overview
19. eFuse Controller

- The ESP32 has a number of eFuses which store system parameters. Fundamentally, an eFuse is a single bit of non-volatile memory with the restriction that once an eFuse bit is programmed to 1, it can never be reverted to 0. Software can instruct the eFuse Controller to program each bit for each system parameter as needed.

Some of these system parameters can be read by software using the eFuse Controller. Some of the system parameters are also directly used by hardware modules.

Features:

- Configuration of 26 system parameters
- Optional write-protection
- Optional software-read-protection

Further information about eFuse technology can be found in the following link https://en.wikipedia.org/wiki/EFUSE
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About "AES Accelerator" on the ESP32 Technical Reference Manual
« Reply #20 on: March 19, 2018, 08:05:55 PM »
Overview
20. AES Accelerator

- The AES Accelerator (Hardware support) speeds up AES operations significantly, compared to AES algorithms implemented solely in software. The AES Accelerator supports six algorithms of FIPS PUB 197, specifically AES-128, AES-192 and AES-256 encryption and decryption.

AES refers to Advanced Encryption Standard wich consist on improving the speed of applications performing encryption and decryption.

For further information about AES follow the link https://es.wikipedia.org/wiki/Advanced_Encryption_Standard


« Last Edit: March 19, 2018, 08:30:42 PM by BlackByte »
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About "SHA Accelerator" the ESP32 Technical Reference Manual
« Reply #21 on: March 19, 2018, 08:19:15 PM »
Overview
21. SHA Accelerator

- The SHA Accelerator (Hardware support) is included to speed up SHA hashing operations significantly, compared to SHA haching algorithms implemented solely in software. The SHA Accelerator supports four algorithms of FIPS PUB 180-4, specifically SHA-1, SHA-256, SHA-384 and SHA-512.

The SHA "Secure Hash Algorithms" are a family of cryptographic hash functions

For further information about SHA follow the link https://en.wikipedia.org/wiki/Secure_Hash_Algorithms



« Last Edit: March 20, 2018, 04:22:11 PM by BlackByte »
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About "RSA Accelerator" the ESP32 Technical Reference Manual
« Reply #22 on: March 20, 2018, 04:56:04 PM »
Overview
22. RSA Accelerator

- The RSA Accelerator provides hardware support for multiple precision arithmetic operations used in RSA asymmetric cipher algorithms.

- Sometimes, multiple precision arithmetic is also called "bignum arithmetic", "bigint arithmetic" or "arbitrary precision arithmetic".

RSA refers to Rivest, Shamir and Adleman who are the designers of the RSA system who is one of the first public-key cryptosystems

Find out more about RSA in the link https://en.wikipedia.org/wiki/RSA_(cryptosystem)
« Last Edit: March 20, 2018, 04:58:38 PM by BlackByte »
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About "Random Number Generator" the ESP32 Technical Reference Manual
« Reply #23 on: March 20, 2018, 05:09:37 PM »
Overview
23. Random Number Generator

- The ESP32 contains a true random number generator, whose values can be used as a basis for cryptographical operations, among other things.

Find more information about random number generation here https://en.wikipedia.org/wiki/Random_number_generation
« Last Edit: March 21, 2018, 05:36:05 PM by BlackByte »
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About "Flash Encryption/Decryption" on the ESP32
« Reply #24 on: March 20, 2018, 05:55:34 PM »
Overview
24. Flash Encryption/Decryption

- Many variants of the ESP32 must store programs and data in external flash memory. The external flash memory chip is likely to contain proprietary firmware and sensitive user data, such as credentials for gaining access to a private network. The Flash Encryption block can encrypt code and write encrypted code to off-chip flash memory for enhanced hardware security. When the CPU reads off-chip flash through the cache, the Flash Decryption block can automatically decrypt instructions and data read from it, thus providing hardware-based security for application code.
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About "PId/MPU/MMU" on the ESP32.
« Reply #25 on: March 21, 2018, 06:00:15 PM »
Overview
25. PId/MPU/MMU

- Every perihperal and memory section in the ESP32 is accessed through either an MMU(Memory Management Unit) or an MPU(Memory Protection Unit). An MPU can allow or disallow the access of an application to a memory range or peripheral, depending of what kind of permission the OS has given to that particular application. An MMU can perform the same operation, as well as a virtual-to-physical memory address translation. This can be used to map an internal or external memory range to a certain virtual memory area. These mappings can be application-specific. Therefore, each application can be adjusted and have the memory configuration that is necessary for it to run properly. To differentiate between the OS and applications, there are eight Process Identifiers (or PIDs) that each application, or OS, can run. Furthermore, each application, or OS, is equipped with their own sets of mappings and rights.
« Last Edit: March 21, 2018, 07:41:22 PM by BlackByte »
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About "PId Controller" on the ESP32 Technical Reference Manual
« Reply #26 on: March 21, 2018, 08:05:10 PM »
Overview
26. PId Controller

- The ESP32 is a dual core device and is capable of running and managing multiple processes. The PId Controller supports switching of PId when a process switch occurs. In addition to PId management, the PId Controller also facilitates management of nested interrupts by recording execution status just before an interrupt service routine is executed. This enables the user application to manage process switches and nested interrupts more efficiently.
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About "On-Chip Sensors and Analog Signal Processing" on the ESP32.
« Reply #27 on: March 21, 2018, 08:44:35 PM »
Overview
27. On-Chip Sensors and Analog Signal Processing

- ESP32 has three types of built-in sensors for various applications: a capacitive touch sensor with up to 10 inputs, a Hall effect sensor and a temperature sensor.

- The processing of analog signals is done by two successive approximation ADCs (SAR ADC). There are five controllers dedicated to operating ADCs. This provides flexibility when it comes to converting analog inputs in both high-performance and low-power modes, with minimum processor overhead.

- there is an aattractive complement to the input of SAR ADC1, which processes small signals - the low noise analog amplifier with an adjustable amplification ratio.

- ESP32 is also capable of generating analog signals, using two independent DACs and a cosine waveform generator.

Find more information about capacitive sensing here https://en.wikipedia.org/wiki/Capacitive_sensing

Find more information about hall sensor here https://en.wikipedia.org/wiki/Hall_effect_sensor
« Last Edit: March 21, 2018, 08:46:07 PM by BlackByte »
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About "ULP Co-processor" on the ESP32 Technical Reference Manual
« Reply #28 on: March 22, 2018, 04:09:13 PM »
Overview
28. ULP Co-Processor

- The ULP co-processor is an ultra-low-power processor that remains powered on during the Deep-sleep mode of the main SoC. Hence, the developer can store in the RTC memory a program for the ULP co-processor to access peripheral devices, internal sensors and RTC registers during deep sleep. This is useful for designing applications where the CPU needs to be woken up by an external event, or timer, or a combination of these, while maintaining minimal power consumption.
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About "Low-Power Management" on the ESP32 Technical Reference Manual
« Reply #29 on: March 22, 2018, 05:10:18 PM »
Overview
29. Low-Power Management

- ESP32 offers efficient and flixible power-management technology to achieve the best balance between power consumption, wakeup latency and available wakeup sources. Users can select out of five predefined power modes of the main processors to suit specific needs of the application. In addition, to save power in power-sensitive applications, control may be executed by the Ultra-Low-Power co-processor (ULP co-processor), while the main processors are in Deep-sleep mode.
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