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Espressif ESP32 chip => Studying the ESP32 features => Topic started by: BlackByte on February 28, 2018, 10:34:50 PM

Title: About the ESP32 Technical Reference Manual
Post by: BlackByte on February 28, 2018, 10:34:50 PM
Here is the main content of the technical manual for the ESP32.

In this topic we will study the ESP32 features.

1.- System and Memory Ready
2.- Interrupt Matrix Ready
3.- Reset and Clock Ready
4.- IO_MUX and GPIO Matrix Ready
5.- DPort Register Ready
6.- DMA Controller Ready
7.- SPI Ready
8.- SDIO Slave Ready
9.- SD/MMC Host Controller Ready
10.- I2C Ready
11.- I2S Ready
12.- UART Controllers Ready
13.- LED_PWM Ready
14.- Remote Controller Peripheral Ready
15.- MCPWM Ready
16.- PULSE_CNP Ready
17.- 64-bit Timers Ready
18.- Watchdog Timers Ready
19.- eFuse Controller Ready
20.- AES Accelerator Ready
21.- SHA Accelerator Ready
22.- RSA Accelerator Ready
23.- Random Number Generator Ready
24.- Flash Encryption/Decryption Ready
25.- PID/MPU/MMU Ready
26.- PID Controller Ready
27.- On-Chip Sensors and Analog Signal Processing Ready
28.- ULP Co-processor Ready
29.- Low-Power Management Ready

Once you have learn a little bit more about ESP32 features you can learn how to install the ESP32 Development framework in the link below.

ESP32 APIs and Toolchain Installation http://thebytespace.cl/smf/index.php?topic=18.0 (http://thebytespace.cl/smf/index.php?topic=18.0)

Why i present this information?

- Because i have decided to learn this tools in this year, and i have some experience programming other tools before, so i decided to start this study knowing what this caracteristics are one by one, and then going deeper on every one after, this way we will be going from general to specific, this way we can do a mental image about the system from beginning.

- If this is your first time programming a MCU (Micro controller Unit) and you want to undestand more about what is going on here, i recommend you to learn about Microcontroller architecture, and what this things are and what are they  capable of.
Title: About "System and Memory" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 02, 2018, 04:30:48 AM
Overview
1.- System and Memory.

- So ESP32 is a dual-core system, both Harvard architecture (Xtensa LX6 CPUs).

- Memory (both of them, embedded and external memory) and peripherals are located on the data bus and/or the instruction bus of these CPUs.

- Theaddress mapping of two CPUs is symmetric, that means both access the same memory with same addresses (with some minor exceptions).

- Many perihperals in the system can access embedded memory via DMA (Direct Memory Access).

- There is a protocol CPU named 'PRO_CPU' and an application CPU named 'APP_CPU' and they are however interchangeable for most purposes.
Title: About "Imterrupt Matrix" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 02, 2018, 02:56:10 PM
Overview
2.- Interrupt Matrix

- The Interrupt Matrix embedded in the ESP32 independently allocates peripheral interrupt sources to the two CPUs perihperal interrupts so this way is flexible to meet many different needs.

- It acepts 71 peripheral interrupt sources as input.

- Every CPU can generates 26 peripheral interrupt sources as output (52 in total).

- There is an "NMI" interrupt mask

- You can query the current interrupt status of perihperal interrupt sources.
Title: About "Reset and CLock" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 02, 2018, 03:29:43 PM
Overview
3. Reset and Clock

3.1 System Reset

- ESP32 has three reset levels:
 
 1- System itself (Core + RTC)
 2- Only Core reset (CPU + WIFI + Bluetooth + DIG GPIO + PERI). 'subsystem'
 3- Just CPU reset (Central Processing Unit) 'subsystem'

- In system reset, all the registers on the chip, including those of the RTC are reset.

- In core reset, all the digital registers, including CPU cores, external GPIO and digital GPIO. (Not the RTC registers).

- In CPU reset, only the registers of the CPUs are reset 'both or just one'.

**Reset could mean set to default values or clear or erased**

3.2 System Clock.

 - ESP32 integrates multiple clock sources for the CPU cores, perihperals and the RTC.
This clocks can be configured to meet different requirements. (High Speed Clocks, Low Power Clocks and Audio CLock).
Title: About "IO_MUX" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 03, 2018, 04:03:29 PM
Overview
4. Input Output Multiplexor (IO_MUX) and General Prupose Input Output Matrix (GPIO Matrix)

The esp32 has 34 physical pads for input or output called GPIO "General Purpose Input Output".

Each pad can be used as a general-purpose Input/Output, or be connected to an internal peripheral signal. The IO_MUX (IO Multiplexor), RTC IO_MUX (RTC IO Multiplexor) and GPIO matrix are responsible for routing signals from the peripherals to GPIO pads providing configurable Input/outputs.
Title: About "DPort Register" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 05, 2018, 01:55:23 AM
Overview
5. DPort Register.

The DPort registers control clock management (clock gating), power management, and the configuration of peripherals and core system modules.

"The system configures each module via the configuration registers in DPort Register."

DPort registers correspond to different peripherals blocks and core modules:

 - System and memory
 - Reset and clock
 - Interrupt matrix
 - DMA (Direct Memory Access)
 - PID/MPU/MMU
 - Peripheral clock gating and reset.
Title: About "DMA Controller" the ESP32 Technical Reference Manual
Post by: BlackByte on March 05, 2018, 02:50:13 AM
Overview
6. DMA controller

 Direct Memory Access is used for high-speed data transfer between perihperals and memory as well as memory to memory.

 Data can be quickly moved by DMA without any CPU intervention, thus allowing for more efficient use of the cores for data processing.

 In the ESP32, 13 peripherals are capable of DMA for data transfer, namely:

 - UART(0,1,2)
 - SPI(1,2,3)
 - I2S(0,1)
 - SDIO slave
 - SD/MMC host
 - EMAC
 - BT
 - Wi-Fi
Title: About "SPI" the ESP32 Technical Reference Manual
Post by: BlackByte on March 08, 2018, 07:10:07 PM
Overview
7.SPI (Serial Peripheral Interface)

ESP32 integrates four SPI controllers. (SPI<0,1,2,3>)

SPI<0> is used as a buffer for accessing external memory.
SPI<1> can be used as a MASTER
SPI<2> can be configured as either a MASTER or a SLAVE.
SPI<3> can be configured as either a MASTER or a SLAVE.

When used as a MASTER, each SPI controller can drive multiple CS signals (CS0  - CS2) to activate multiple SLAVES.

Controllers SPI1,SPI2 & SPI3 share two DMA channels.(chan0 & chan1).

-

The SPI controller supports four-lines.
- MOSI (Master Output - Slave Input)
- MISO (Master Input - Slave Output)
- CS (Chip Select)
- CLK (Clock)

The full-duplex uses four of them. (MOSI/MISO/CS/CLK)
The half-duplex uses three of them. (MOSI/CS/CLK).
in GP-SPI mode.

In QSPI mode a SPI controller accesses the flash or SRAM by using signal buses D, Q, CS0-CS2, CLK, WP and HD as a four-bit parallel SPI bus.

(Consult "Table 24: SPI Signal and Pin Signal Function Mapping)
Technical reference manual Page 116.

Find more about SPI port. https://es.wikipedia.org/wiki/Serial_Peripheral_Interface
Title: About "SDIO Slave" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 09, 2018, 03:55:26 PM
Overview
8.SDIO Slave (Secure Digital Input/Output)

- The ESP32 features hardware support for the industry-standard Secure Digital device interface that conforms to the SDIO Specification Version 2.0. This allows a host controller to access the ESP32 via an SDIO bus protocol, enabling high-speed data transfer.

- The SDIO interface may be used to read ESP32 SDIO registers directly and access shared memory via DMA, thus reducing processing overhead while maintaining high performance.

Find out more about SDIO here https://en.wikipedia.org/wiki/Secure_Digital#SDIO_cards

Find out more about SDIO Spacification here https://www.sdcard.org/downloads/pls/


Title: Re: About the ESP32 Technical Reference Manual
Post by: BlackByte on March 09, 2018, 09:52:09 PM
Overview
9. SD/MMC Host Controller

- The ESP32 memory card interface controller provides a hardware interface between the Advanced Peripheral Bus (APB) and an external memory device. The memory card interface alllows the ESP32 to be connected to SDIO memory cards, MMC cards (MultiMediaCard) and devices with a CE-ATA interface. It supports two external cards (Card0 and Card1).

Found more about MMC card here https://en.wikipedia.org/wiki/MultiMediaCard
Title: Re: About the ESP32 Technical Reference Manual
Post by: BlackByte on March 09, 2018, 10:04:14 PM
Overview
10. I2C Controller

- An I2C (Inter-Integrated Circuit) bus can be used for communication with several external devices connected to the same bus as ESP32. The ESP32 has dedicated hardware to communicate with peripherals on the I2C bus.

Found out more about I2C communication here https://en.wikipedia.org/wiki/I%C2%B2C
Title: Re: About the ESP32 Technical Reference Manual
Post by: BlackByte on March 10, 2018, 07:34:50 PM
Overview
11. I2S (Integrated Interchip Sound)

- The I2S bus provides a flexible communication interface for streaming digital data in multimedia applications, especially digital audio applications. The ESP32 includes two I2S interfaces: I2S0 & I2S1.

- The I2S standard bus define three signals:
  .clock signal
  .serial data signal
  .channel selection signal

- A basic I2S data bus has one master and one slave. The roles remain unchanged throughout the communication.

- The I2S modules on the ESP32 provide separate transmit and receive channels for high performance.

- there are two independent I2S modules embedded in ESP32. Each I2S module contains a Tx(transmit) unit and a Rx(receive) unit. Both the Tx unit and the Rx unit have a three-wire interface that includes a clock line, a channel selection line and a serial data line. The serial data line of the Tx unit is fixed as output, and the serial data line of the receive unit is fixed as input. The clock line an the channel selection line of the Tx and Rx units can be configured to both master transmitting mode and slave receiving mode. In the LCD mode, the serial data line extends to the parallel data bus. Both Tx uni and Rx unit have a 32-bit-wide FIFO with a depth of 64. Besides, only I2S0 supports on-chip DAC/ADC modes, as well as receiving and transmitting PDM signals.

Learn more about PDM modulation here https://en.wikipedia.org/wiki/Pulse-density_modulation

Learn more about I2S here https://en.wikipedia.org/wiki/I%C2%B2S

Title: UART Controllers on ESP32 <i>Overview</i>
Post by: BlackByte on March 12, 2018, 03:11:47 AM
Overview
12. UART Controllers

Embedded applications often require a simple method of exchanging data between devices that need minimal system resources. The Universal Asynchronous Receiver/Transmitter (UART) is one such standard that can realize a flexible full-duplex data exchange among different devices. The three UART controllers available on a chip are compatible with UART-enabled devices from various manufacturers. The UART can also carry out an irDA(Infrared Data Exchange), or function as RS-485 modem.

Find out more about UART here https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter (https://en.wikipedia.org/wiki/Universal_asynchronous_receiver-transmitter)

All UART controllers integrated in the ESP32 feature an identical set of registers for ease of programming and flexibility.
Title: Re: About the ESP32 Technical Reference Manual
Post by: BlackByte on March 14, 2018, 02:17:24 PM
Overview
13. LED_PWM

- The LED_PWM controller is primarily designed to control the intensity of LEDs (Light Emitting Diode), although it can be used to generate PWM (Pulse Width Modulation) signals for other purposes as well. It has 16 channels which can generate independent waveforms that can be used to drive RGB LED devices (Red, Green & Blue color Led). For maximum flexibility, the high-speed as well as the low-speed channels can be driven  from one of four high-speed/low-speed timers. The PWM controller also has the ability to automatically increase or decrease the duty cycle gradually, allowing for fades without any processor interference. To increase resolution, the LED_PWM controller is also able to dither between two values, when a fractional PWM value is configured.

The LED_PWM controller has eight high-speed and eight low-speed PWM generators. These channels can be driven from four timers.

The eight channels (high and low speed) in the technical manual for the ESP32 are referred to as:


The four timers (high and low speed) in the technical manual for the ESP32 are referred to as:


Find out more about PWM here https://en.wikipedia.org/wiki/Pulse-width_modulation (https://en.wikipedia.org/wiki/Pulse-width_modulation)
Title: About the ESP32 Technical Reference Manual
Post by: BlackByte on March 14, 2018, 04:50:14 PM
Overview
14. Remote Controller Peripheral

- The RMT (Remote Control) module is primarily designed to send and receive infrared remote control signals that use on-off-keying of a carrier frequency, but due to its design it can be used to generate various types of signals. An RMT transmitter does this by reading consecutive duration values for an active and inactive output from the built-in RAM block, optionally modulating it with a carrier wave. A receiver will inspect its input signal, optionally filtering it, and will place the lengths of time the signal is active and inactive in the RAM block.

- The RMT has eight channels.
Title: About the ESP32 'MCPWM' from Manual
Post by: BlackByte on March 14, 2018, 05:12:44 PM
Overview
15. MCPWM

- The Motor Control PWM (MCPWM) peripheral is intended for motor and power control.

- It provides six PWM outputs that can be set up to operate in several topologies.

- One common topology uses a pair of PWM outputs driving an H-bridge to control motor rotation speed and rotation direction.

- The timing an control resources inside are allocated into two major types of submodules: PWM timers and PWM operators.

- Each PWM timer provides timing references that can either run freely or be synced to other timers or external sources.

- Each PWM operator has all necessary control resources to generate waveform pairs for one PWM channel.

- The MCPWM peripheral also contains a dedicated capture submodule that is used in systems where accurate timing of external events is important.

- ESP32 contains two MCPWM peripherals: MCPWM0 and MCPWM1. Their control registers are located in 4-KB memory blocks starting at memory locations 0x3FF5E000 and 0x3FF6C000 respectively.



Learn more about H-bdrige herehttps://en.wikipedia.org/wiki/H_bridge (https://en.wikipedia.org/wiki/H_bridge)
Title: About "PULSE_CNT" in the ESP32 Technical Reference Manual
Post by: BlackByte on March 16, 2018, 02:33:46 PM
Overview
16.PULSE_CNT

- The Pulse Counter module is designed to count the number of rising and/or falling edges of an input signal. Each pulse counter unit has a 16-bit signed counter register and two channels that can be configured to either increment or decrement the counter. Each channel has a signal input that accepts signal edges to be detected, as well as a control input that can be used to enable or disable the signal input. The inputs have optional filters that can be used to discard unwated glitches in the signal.

- The pulse counter has eight independent units, refered to as PULSE_CNT_Un.
Title: About the 64-bit Timers on ESP32 Technical Reference Manual
Post by: BlackByte on March 16, 2018, 02:53:18 PM
Overview
17. 64-bit Timers

- There are four general-purpose timers embedded in the ESP32. They are all 64-bit generic timers based on 16-bit prescalers and 64-bit auto-capable up/down counters.

- The ESP32 contains two timers modules, each containing two timers. The two timers in a block are indicated by an x in TIMGn_Tx; the blocks themselves are indicated by an n.

 The timers feature:
 - A 16-bit clock prescaler, from 2 to 65536.
 - A 64-bit time-base counter.
 - Configurable up/down time-base counter: incrementing or decrementing.
 - Halt and resume of time-base counter.
 - Auto-reload at alarm
 - Software-controlled instant reload.
 - Level and edge interrupt generation.
Title: About "Watchdog Timers" on the ESP32.
Post by: BlackByte on March 16, 2018, 03:31:23 PM
Overview
18. Watchdog Timers

- The ESP32 has three watchdog timers: one in each of the two timer modules (called Main system Watchdog Timer, or MWDT) and one in the RTC module (which is called the RTC Watchdog Timer, or RWDT). These watchdog timers are intended to recover from an unforseen fault (not anticipated or predicted fault), causing the application program to abandon its normal sequence. A watchdog timer has four stages. Each stage may take one out of three or four actions upon the expiry of a programmed period of time for this stage, unless the watchdog is fed or disabled. The actions are: interrupt, CPU reset, core reset and system reset. Only the RWDT can trigger the system reset, and is able to reset the entire chip and the main system including the RTC itself. A timeout value can be set for each stage individually.

- During flash boot, the RWDT and the first MWDT start automatically in order to detect and recover from booting problems.

Further information about Watchdog Timers here https://en.wikipedia.org/wiki/Watchdog_timer (https://en.wikipedia.org/wiki/Watchdog_timer)
Title: About "eFuse Controller" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 16, 2018, 04:04:48 PM
Overview
19. eFuse Controller

- The ESP32 has a number of eFuses which store system parameters. Fundamentally, an eFuse is a single bit of non-volatile memory with the restriction that once an eFuse bit is programmed to 1, it can never be reverted to 0. Software can instruct the eFuse Controller to program each bit for each system parameter as needed.

Some of these system parameters can be read by software using the eFuse Controller. Some of the system parameters are also directly used by hardware modules.

Features:

- Configuration of 26 system parameters
- Optional write-protection
- Optional software-read-protection

Further information about eFuse technology can be found in the following link https://en.wikipedia.org/wiki/EFUSE (https://en.wikipedia.org/wiki/EFUSE)
Title: About "AES Accelerator" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 19, 2018, 08:05:55 PM
Overview
20. AES Accelerator

- The AES Accelerator (Hardware support) speeds up AES operations significantly, compared to AES algorithms implemented solely in software. The AES Accelerator supports six algorithms of FIPS PUB 197, specifically AES-128, AES-192 and AES-256 encryption and decryption.

AES refers to Advanced Encryption Standard wich consist on improving the speed of applications performing encryption and decryption.

For further information about AES follow the link https://es.wikipedia.org/wiki/Advanced_Encryption_Standard (https://es.wikipedia.org/wiki/Advanced_Encryption_Standard)


Title: About "SHA Accelerator" the ESP32 Technical Reference Manual
Post by: BlackByte on March 19, 2018, 08:19:15 PM
Overview
21. SHA Accelerator

- The SHA Accelerator (Hardware support) is included to speed up SHA hashing operations significantly, compared to SHA haching algorithms implemented solely in software. The SHA Accelerator supports four algorithms of FIPS PUB 180-4, specifically SHA-1, SHA-256, SHA-384 and SHA-512.

The SHA "Secure Hash Algorithms" are a family of cryptographic hash functions

For further information about SHA follow the link https://en.wikipedia.org/wiki/Secure_Hash_Algorithms (https://en.wikipedia.org/wiki/Secure_Hash_Algorithms)



Title: About "RSA Accelerator" the ESP32 Technical Reference Manual
Post by: BlackByte on March 20, 2018, 04:56:04 PM
Overview
22. RSA Accelerator

- The RSA Accelerator provides hardware support for multiple precision arithmetic operations used in RSA asymmetric cipher algorithms.

- Sometimes, multiple precision arithmetic is also called "bignum arithmetic", "bigint arithmetic" or "arbitrary precision arithmetic".

RSA refers to Rivest, Shamir and Adleman who are the designers of the RSA system who is one of the first public-key cryptosystems

Find out more about RSA in the link https://en.wikipedia.org/wiki/RSA_(cryptosystem) (https://en.wikipedia.org/wiki/RSA_(cryptosystem))
Title: About "Random Number Generator" the ESP32 Technical Reference Manual
Post by: BlackByte on March 20, 2018, 05:09:37 PM
Overview
23. Random Number Generator

- The ESP32 contains a true random number generator, whose values can be used as a basis for cryptographical operations, among other things.

Find more information about random number generation here https://en.wikipedia.org/wiki/Random_number_generation (https://en.wikipedia.org/wiki/Random_number_generation)
Title: About "Flash Encryption/Decryption" on the ESP32
Post by: BlackByte on March 20, 2018, 05:55:34 PM
Overview
24. Flash Encryption/Decryption

- Many variants of the ESP32 must store programs and data in external flash memory. The external flash memory chip is likely to contain proprietary firmware and sensitive user data, such as credentials for gaining access to a private network. The Flash Encryption block can encrypt code and write encrypted code to off-chip flash memory for enhanced hardware security. When the CPU reads off-chip flash through the cache, the Flash Decryption block can automatically decrypt instructions and data read from it, thus providing hardware-based security for application code.
Title: About "PId/MPU/MMU" on the ESP32.
Post by: BlackByte on March 21, 2018, 06:00:15 PM
Overview
25. PId/MPU/MMU

- Every perihperal and memory section in the ESP32 is accessed through either an MMU(Memory Management Unit) or an MPU(Memory Protection Unit). An MPU can allow or disallow the access of an application to a memory range or peripheral, depending of what kind of permission the OS has given to that particular application. An MMU can perform the same operation, as well as a virtual-to-physical memory address translation. This can be used to map an internal or external memory range to a certain virtual memory area. These mappings can be application-specific. Therefore, each application can be adjusted and have the memory configuration that is necessary for it to run properly. To differentiate between the OS and applications, there are eight Process Identifiers (or PIDs) that each application, or OS, can run. Furthermore, each application, or OS, is equipped with their own sets of mappings and rights.
Title: About "PId Controller" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 21, 2018, 08:05:10 PM
Overview
26. PId Controller

- The ESP32 is a dual core device and is capable of running and managing multiple processes. The PId Controller supports switching of PId when a process switch occurs. In addition to PId management, the PId Controller also facilitates management of nested interrupts by recording execution status just before an interrupt service routine is executed. This enables the user application to manage process switches and nested interrupts more efficiently.
Title: About "On-Chip Sensors and Analog Signal Processing" on the ESP32.
Post by: BlackByte on March 21, 2018, 08:44:35 PM
Overview
27. On-Chip Sensors and Analog Signal Processing

- ESP32 has three types of built-in sensors for various applications: a capacitive touch sensor with up to 10 inputs, a Hall effect sensor and a temperature sensor.

- The processing of analog signals is done by two successive approximation ADCs (SAR ADC). There are five controllers dedicated to operating ADCs. This provides flexibility when it comes to converting analog inputs in both high-performance and low-power modes, with minimum processor overhead.

- there is an aattractive complement to the input of SAR ADC1, which processes small signals - the low noise analog amplifier with an adjustable amplification ratio.

- ESP32 is also capable of generating analog signals, using two independent DACs and a cosine waveform generator.

Find more information about capacitive sensing here https://en.wikipedia.org/wiki/Capacitive_sensing (https://en.wikipedia.org/wiki/Capacitive_sensing)

Find more information about hall sensor here https://en.wikipedia.org/wiki/Hall_effect_sensor (https://en.wikipedia.org/wiki/Hall_effect_sensor)
Title: About "ULP Co-processor" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 22, 2018, 04:09:13 PM
Overview
28. ULP Co-Processor

- The ULP co-processor is an ultra-low-power processor that remains powered on during the Deep-sleep mode of the main SoC. Hence, the developer can store in the RTC memory a program for the ULP co-processor to access peripheral devices, internal sensors and RTC registers during deep sleep. This is useful for designing applications where the CPU needs to be woken up by an external event, or timer, or a combination of these, while maintaining minimal power consumption.
Title: About "Low-Power Management" on the ESP32 Technical Reference Manual
Post by: BlackByte on March 22, 2018, 05:10:18 PM
Overview
29. Low-Power Management

- ESP32 offers efficient and flixible power-management technology to achieve the best balance between power consumption, wakeup latency and available wakeup sources. Users can select out of five predefined power modes of the main processors to suit specific needs of the application. In addition, to save power in power-sensitive applications, control may be executed by the Ultra-Low-Power co-processor (ULP co-processor), while the main processors are in Deep-sleep mode.
Title: Re: About the ESP32 Technical Reference Manual
Post by: kartmanfulse on July 26, 2019, 04:00:39 PM
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Title: Re: About the ESP32 Technical Reference Manual
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